Formal Verification of Verilog HDL with Yosys-SMTBMC (33c3)

Yosys is a free and open source Verilog synthesis tool and more. It gained prominence last year because of its role as synthesis tool in the Project IceStorm FOSS Verilog-to-bitstream flow for iCE40 FPGAs. This presentation however dives into the Yosys-SMTBMC formal verification flow that can be used for verifying formal properties using bounded model checks and/or temporal induction. about this event: https://fahrplan.events.ccc.de/congress/2016/Fahrplan/events/7922.html